VLSI Engineer - Verification

  • Wipro
  • South West Pena,Malaysia
  • Aug 14, 2018
Permanent

Job Description


Mandatory Skills:
VLSI-VERIFICATION PLANNING

Desirable Skills:
VLSI HVL Verification

Job Description:

Good understanding ofdigital design

Good working knowledgeon any one of the leading verification methodology UVM/OVM

Proficient in systemVerilog, Verilog and C language

Knowledge on atleast 2of the listed protocols Pcie, Ethernet, USB, DDR, AXI, SATA, SPI

Knowledge on UPF flow, debug.

Well organized,methodical and detail oriented

Good debugging skills

Proficiency in English Language is Desirable

Roles & Responsibilities:
Minimum Experience Required: 3-5 YEARS
Mandatory Skills: VLSI-VERIFICATION PLANNING VLSI HDL Verification, VLSI-VERIFICATION PLANNING, VLSI HVL Verification
Desirable Skills: VLSI HVL Verification
Language Skills: English Language