VLSI Digital Design And Verification Architect

  • Wipro
  • Bengaluru,India
  • Jul 07, 2018

Job Description

Mandatory Skills:
System Verilog - SV

Job Description:

Key skills required for the job are:
  • System Verilog - SV-L3 (Mandatory)

  VLSI Technical engineer with 8-12 years of experience in Functional verification 


He/she should have strong knowledge of following   

Working experience in IP / SoC verification Expertise to develop block level / system level verification environments using System Verilog and UVM is mandatory. Expertise  to develop BFMs / Checkers / monitors / Scoreboards Must have developed block/system level verification plans and tests. Must have capability to debug test failures to find the root cause. Experience in constrained random testing is a plus. Experience in IEEE Ethernet/T11 Fibre channel PCS  is mandatory. Knowledge of 25G/50G Ethernet or 64G/128G Fibre channel modes is plus . Gate-level simulations Knowledge of scripting languages like Perl, Tcl 

CAD Tools : Synopsys   

Education Qualification: Bachelors/Master s in Electronics/Computer Engg 

Minimum work experience:5 - 8 Years

Roles & Responsibilities:
Minimum Experience Required: 8-10 YEARS
Mandatory Skills: System Verilog - SV VLSI Physical Verification, VLSI-VERIFICATION PLANNING, Hardware Designing, ASIC Design
Desirable Skills:
Language Skills: English Language