Project Lead VLSI

  • Wipro
  • Bengaluru,India
  • Jul 04, 2018
Permanent

Job Description


Mandatory Skills:
ASIC Design

Job Description:

Key skills required for the job are:

FPGA/ASIC RTL 

Design and development of digital HW modules (on FPGA/ASIC using Verilog) for 3GPP 5G NR wireless modem technologies. Responsible for designing, modeling, verifying and integrating the digital sub-systems implemented on the state of art FPGAs/ASICs. 

Areas of interest are (expertize in any one of them): 

Domain (a): RTL design for digital signal processing logic design (in Verilog), like filter, fft, matrix operations, control, etc.

Domain (b): FPGA, Ethernet packet processing (hardware acceleration), (de-)packetizing modem data for e-CPRI.

Domain (c): RTL design for SERDES interfaces - FPGA systems.

  • ASIC Design-L3 (Mandatory)

As a Lead, you are responsible for managing a small team of analysts, developers, testers or engineers and drive delivery of a small module within a project (Delivery/Maintenence/Testing) You may serve as entry level specialist with expertise in particular technology/industry domain/a process / application / product. You are responsible for functional/technical track of a project.

Minimum work experience:5 - 8 Years

Roles & Responsibilities:
Minimum Experience Required:
Mandatory Skills: ASIC Design Project Management
Desirable Skills:
Language Skills: English Language