VLSI Digital Design And Verification Architect

  • Wipro
  • Dallas - Texas,USA
  • Jun 02, 2018
Permanent

Job Description


Mandatory Skills:
VLSI-VERIFICATION PLANNING

Desirable Skills:
System Verilog - SV, Processor Architecture

Job Description:

Should have SoC and IP level Functional Verification experience of 6-10 Yrs. 

Should have good ASIC/SOC System Level Architecture knowledge

Strong understanding of verification process from test plan to coverage completion

Knowledge of processor architecture and verification is a plus.

Strong communication and Analytical skills

Proficient in debugging and issue fixing 

Ability to lead and coordinate multi-site teams.

Expert in System Verilog based Test Bench Architecture development 

Good hands-on on SV-UVM based Test environment components implementation such as SV Testbench, drivers, monitors, scoreboards, checkers

Familiar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques.

Experience in setup and debug of gate level simulation

Knowledge of low power verification

DFX validation is a plus

Knowledge of synopsys tools is desired

Strong working knowledge of any of these protocols: DDR, USB, PCIe, Ethernet, SATA,AXI...

Roles & Responsibilities:
Minimum Experience Required: 8-10 YEARS
Mandatory Skills: VLSI-VERIFICATION PLANNING VLSI Physical Verification, VLSI-VERIFICATION PLANNING, Hardware Designing, ASIC Design
Desirable Skills: System Verilog - SV, Processor Architecture
Language Skills: English Language