VLSI Tech Lead - Verification

  • Wipro
  • Bengaluru,India
  • May 23, 2018

Job Description

Mandatory Skills:
System Verilog - SV

Job Description:

Key skills required for the job are: 
  • System Verilog - SV-L3 (Mandatory)

Experience level must be between 4-8 years.


Must haves:


Good understanding of digital design


Good working knowledge on any one of the leadingverification methodology UVM/VMM/Vera


Proficient in system Verilog, Verilog and C language


Knowledge on atleast 2 of the listed protocols PCIe,Ethernet, USB, DDR, AXI


Well organized, methodical and detail oriented


Sound logical and analytical skills


Good to have:


Knowledge on ARM based sub-system


Scripting/Automation knowledge perl or bash


Knowledge on network protocols


Minimum work experience:5 - 8 Years

Roles & Responsibilities:
Minimum Experience Required: 5-8 YEARS
Mandatory Skills: System Verilog - SV Gate Level Simulation - GLS, VLSI HDL Verification, VLSI-VERIFICATION PLANNING, VLSI HVL Verification, Hardware Modelling
Desirable Skills:
Language Skills: English Language