VLSI HVL Verification
System Verilog - SV, Gate Level Simulation - GLS
- Should have SoC and IP level Functional Verificationexperience of 2-3 Yrs.
- Experience in SystemVerilog based verification
- Good hands-on on SV-UVM based Test environmentcomponents implementation such as SV Testbench, drivers, monitors,scoreboards, checkers
- Familiar with System Verilog Assertions, Code andFunctional Coverage and Formal verification techniques.
- Working knowledge of any of these protocols: DDR, USB,PCIe, Ethernet, SATA,AXI...
- Experience in working with gate level simulation
- Knowledge of synopsys tools is desired
- Strong communication and Analytical skills
- Proficient in debugging and issue fixing
Roles & Responsibilities: Minimum Experience Required:
1-3 YEARS Mandatory Skills:
VLSI HVL Verification HDL Verification, VLSI HVL Verification, VLSI HDL Verification Desirable Skills:
Gate Level Simulation - GLS, System Verilog - SV Language Skills: