System Verilog - SV, Gate Level Simulation - GLS
- Should have SoC and IP level Functional Verificationexperience of 6-10 Yrs.
- Expert in System Verilog based Test Bench Architecturedevelopment.
- Good hands-on on SV-UVM based Test environmentcomponents implementation such as SV Testbench, drivers, monitors,scoreboards, checkers
- Should have good ASIC/SOC System Level Architectureknowledge
- DFX validation
- Familiar with System Verilog Assertions, Code andFunctional Coverage and Formal verification techniques.
- Strong working knowledge of any of these protocols: DDR,USB, PCIe, Ethernet, SATA,AXI...
- Experience in setup and debug of gate level simulation
- Knowledge of low power verification
- Knowledge of synopsys tools is desired
- Strong understanding of verification process from testplan to coverage completion
- Strong communication and Analytical skills
- Proficient in debugging and issue fixing
- Good Customer Orientation
Roles & Responsibilities: Minimum Experience Required:
8-10 YEARS Mandatory Skills:
VLSI-VERIFICATION PLANNING VLSI Physical Verification, VLSI-VERIFICATION PLANNING, Hardware Designing, ASIC Design Desirable Skills:
System Verilog - SV, Gate Level Simulation - GLS Language Skills: