VLSI Engineer - Verification

  • Wipro
  • New York City - New York,USA
  • Apr 25, 2018

Job Description

Mandatory Skills:
VLSI HVL Verification

Desirable Skills:
System Verilog - SV, Gate Level Simulation - GLS

Job Description:

  • Should have SoC and IP level Functional Verificationexperience of 3-6   Yrs. 
  • Experience   in SystemVerilog based Test Bench Architecture development 
  • Good hands-on on SV-UVM based Test environmentcomponents implementation such as  SV Testbench, drivers, monitors,scoreboards, checkers
  • DFX validation
  • Familiar with System Verilog Assertions, Code andFunctional Coverage and Formal verification techniques.
  • Strong working knowledge of any of these protocols: DDR,USB, PCIe, Ethernet, SATA,AXI...
  • Experience in working with gate level simulation
  • Knowledge of low power verification
  • Knowledge of synopsys tools is desired
  • Strong understanding of verification process from testplan to coverage completion
  • Strong communication and Analytical skills
  • Proficient in debugging and issue fixing 

Roles & Responsibilities:
Minimum Experience Required: 3-5 YEARS
Mandatory Skills: VLSI HVL Verification VLSI-VERIFICATION PLANNING, VLSI HVL Verification, VLSI HDL Verification
Desirable Skills: Gate Level Simulation - GLS, System Verilog - SV
Language Skills: English Language